View ST72T63_1791477.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.8 august 2000 1/109 st7263 low speed usb 8-bit mcu family with up to 16k memory, up to 512 bytes ram, 8-bit adc, wdg, timer, sci & i 2 c datasheet n up to 16kbytes program memory n data ram: up to 512 bytes with 64 bytes stack n run, wait and halt cpu modes n 12 or 24 mhz oscillator n ram retention mode n usb (universal serial bus) interface with dma for low speed applications compliant with usb 1.5 mbs specification (version 1.1) and usb hid specifications (version 1.0) n integrated 3.3v voltage regulator and transceivers n suspend and resume operations n 3 endpoints with programmable in/out configuration n 19 programmable i/o lines with: C 8 high current i/os (10ma at 1.3v) C 2 very high current pure open drain i/os (25ma at 1.5v) C 8 lines individually programmable as interrupt inputs n optional low voltage detector (lvd) n programmable watchdog for system reliab ility n 16-bit timer with: C 2 input captures C 2 output compares C pwm generation capabilities C external clock input n asynchronous serial communications interface (8k and 16k program memory versions only) n i 2 c multi master interface up to 400 khz (16k program memory version only) n 8-bit a/d converter (adc) with 8 channels n fully static operation n 63 basic instructions n 17 main addressing modes n 8x8 unsigned multiply instruction n true bit manipulation n versatile development tools (under windows) including assembler, linker, c-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers table 1. device summary note 1: eprom version for development only so34 (shrink) psdip32 csdip32w features st72631 st72632 st72633 rom - otp (bytes) 16k 8k 4k ram (stack) - bytes 512 (64) 256 (64) peripherals watchdog, 16-bit timer, sci, i 2 c, adc, usb watchdog, 16-bit timer, sci, adc, usb watchdog, 16-bit timer, adc, usb operating supply 4.0v to 5.5v cpu frequency 8 mhz (with 24 mhz oscillator) or 4 mhz (with 12 mhz oscillator) operating temperature 0c to +70c packages so34/sdip32 eprom device st72e631 1 (csdip32w) 1
table of contents 109 2/109 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 eprom/otp program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 eprom erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 clocks and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4 interrupts and power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.1 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 4.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4.2.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 5 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.4 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.6 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6
table of contents 3/109 5.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 5.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.6.5 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.7 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 5.7.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.7.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.8 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 5.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
st7263 4/109 7.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6 low voltage detector (lvd) characteristics . . . . . . . . . . . . . . . . . . . . . . . . 98 7.7 control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.1 usb - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.9 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . 106 9.1 device ordering information and transfer of customer code . . . . . 106 9.2 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3 to get more information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
st7263 5/109 1 general description 1.1 introduction the st7263 microcontrollers form a sub family of the st7 dedicated to usb applications. the de- vices are based on an industry-standard 8-bit core and feature an enhanced instruction set. they op- erate at a 24mhz or 12 mhz oscillator frequency. under software control, the st7263 mcus may be placed in either wait or halt modes, thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8-bit data man- agement, the st7263 mcus feature true bit ma- nipulation, 8x8 unsigned multiplication and indirect addressing modes. the devices include an st7 core, up to 16k program memory, up to 512 bytes ram, 19 i/o lines and the following on-chip pe- ripherals: C usb low speed interface with 3 endpoints with programmable in/out configuration using the dma architecture with embedded 3.3v voltage regulator and transceivers (no external compo- nents are needed). C 8-bit analog-to-digital converter (adc) with 8 multiplexed analog inputs C industry standard asynchronous sci serial inter- face (not on all products - see device summary below) C digital watchdog C 16-bit timer featuring an external clock input, 2 input captures, 2 output compares with pulse generator capabilities C fast i2c multi master interface (not on all prod- ucts - see device summary) C low voltage (lvd) reset ensuring proper power- on or power-off of the device all st7263 mcus are available in rom and otp versions. the st72e631 is the eprom version of the st7263 in csdip32 windowed packages. a specific mode is available to allow programming of the eprom user memory array. this is set by a specific voltage source applied to the v pp /test pin. figure 1. general block diagram 8-bit core alu address and data bus oscin oscout reset port b 16-bit timer port a port c pb[7:0] (8 bits) pc[2:0] (3 bits) oscillator internal clock control ram (256/512 bytes) pa[7:0] (8 bits) v ss v dd power supply sci* program (4k/8k/16k bytes) i 2 c* memory adc (uart) usb sie osc/3 lvd watchdog v ssa v dda v pp /test usb dma usbdp usbdm usbvcc osc/4 or osc/2 (for usb) * not on all products (refer to table 1: device summary)
st7263 6/109 1.2 pin description figure 2. 34-pin so package pinout figure 3. 32-pin sdip package pinout 18 19 20 21 22 23 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd oscout ain4/it5/pb4 (10ma) ain5/it6/pb5 (10ma) v pp /test ain6/it7/pb6 (10ma) ain7/it8/pb7 (10ma) nc reset pc0/rdi pc1/tdo pc2/usboe v ss oscin usbdp v ssa pb0 (10ma) /ain0 pa7/ocmp2/it4 pa6/ocmp1/it3 pa5/icap2/it2 pa4/icap1/it1 pa3/extclk pa2 (25ma) /scl nc nc nc pa1 (25ma) /sda pa0/mco 15 16 17 ain1/pb1 (10ma) ain2/pb2 (10ma) ain3/pb3 (10ma) 34 33 32 v dda usbvcc usbdm * v pp on eprom/otp versions only 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 v dd oscout ain1/pb1/ (10ma) ain2/pb2 (10ma) ain3/pb3 (10ma) ain4/it5/pb4 (10ma) ain5/it6/pb5 (10ma) v pp /test* ain6/it7/pb6 (10ma) pc0/rdi pc1/tdo pc2/usboe v ss oscin ain7/it8/pb7 (10ma) reset v dda usbvcc pb0 (10ma) /ain0 pa7/comp2/it4 pa6/comp1/it3 pa5/icap2/it2 pa4/icap1/it1 pa3/extclk pa2 (25ma) /scl pa1 (25ma) /sda pa0/mco v ssa usbdp usbdm nc nc * v pp on eprom/otp versions only
st7263 7/109 pin description (contd) reset (see note 1): bidirectional. this active low signal forces the initialization of the mcu. this event is the top priority non maskable interrupt. this pin is switched low when the watchdog has triggered or v dd is low. it can be used to reset ex- ternal peripherals. oscin/oscout: input/output oscillator pin. these pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. v pp /test : eprom programming input. this pin must be held low during normal operating modes. v dd /v ss (see note 2): main power supply and ground voltages. v dda /v ssa (see note 2): power supply and ground for analog peripherals. alternate functions : several pins of the i/o ports assume software programmable alternate func- tions as shown in the pin description. note 1 : adding two 100nf decoupling capacitors on reset pin (respectively connected to v dd and v ss ) will significantly improve product electromag- netic susceptibility performances. note 2 : to enhance reliability of operation, it is recommended to connect v dda and v dd together on the application board. the same recommenda- tions apply to v ssa and v ss . table 2. device pin description pin n pin name type level port / control main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp 11v dd s power supply voltage (4v - 5.5v) 2 2 oscout o oscillator output 3 3 oscin i oscillator input 44v ss s digital ground 5 5 pc2/usboe i/o c t x x port c2 usb output enable 6 6 pc1/tdo i/o c t x x port c1 sci transmit data output *) 7 7 pc0/rdi i/o c t x x port c0 sci receive data input *) 8 8 reset i/o x x reset -- 9 nc -- not connected 9 10 pb7/ain7/it8 i/o c t 10ma x xx x port b7 adc analog input 7 10 11 pb6/ain6/it7 i/o c t 10ma x xx x port b6 adc analog input 6 11 12 v pp /test s supply for eprom and test input 12 13 pb5/ain5/it6 i/o c t 10ma x xx x port b5 adc analog input 5 13 14 pb4/ain4/it5 i/o c t 10ma x xx x port b4 adc analog input 4 14 15 pb3/ain3 i/o c t 10ma x xx port b3 adc analog input 3 15 16 pb2/ain2 i/o c t 10ma x xx port b2 adc analog input 2 16 17 pb1/ain1 i/o c t 10ma x xx port b1 adc analog input 1 17 18 pb0/ain0 i/o c t 10ma x xx port b0 adc analog input 0 18 19 pa7/ocmp2/it4 i/o c t x xx port a7 timer output compare 2 19 20 pa6/ocmp1/it3 i/o c t x xx port a6 timer output compare 1
st7263 8/109 *: if the peripheral is present on the device (see table 1 device summary ) legend / abbreviations for figure 2 and table 2 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: 10ma = 10ma high sink (on n-buffer only) 25ma = 25ma very high sink (on n-buffer only) port and control configuration: C input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog C output: od = open drain, pp = push-pull, t = true open drain refer to i/o ports on page 25 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is kept as long as the device is under reset state. 20 21 pa5/icap2/it2 i/o c t x xx port a5 timer input capture 2 21 22 pa4/icap1/it1 i/o c t x xx port a4 timer input capture 1 22 23 pa3/extclk i/o c t x x port a3 timer external clock 23 24 pa2/scl i/o c t 25ma x t port a2 i 2 c serial clock *) -- 25 nc -- not connected 24 26 nc -- not connected 25 27 nc -- not connected 26 28 pa1/sda i/o c t 25ma x t port a1 i 2 c serial data *) 27 29 pa0/mco i/o c t xx port a0 main clock output 28 30 v ssa s analog ground 29 31 usbdp i/o usb bidirectional data (data +) 30 32 usbdm i/o usb bidirectional data (data -) 31 33 usbvcc o usb power supply 32 34 v dda s analog supply voltage pin n pin name type level port / control main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp
st7263 9/109 1.3 external connections the following figure shows the recommended ex- ternal connections for the device. the v pp pin is only used for programming otp and eprom devices and must be tied to ground in user mode. the 10 nf and 0.1 f decoupling capacitors on the power supply lines are a suggested emc per- formance/cost tradeoff. the external reset network is intended to protect the device against parasitic resets, especially in noisy environments. unused i/os should be tied high to avoid any un- necessary power consumption on floating lines. an alternative solution is to program the unused ports as inputs with pull-up. figure 4. recommended external connections v pp v dd v ss oscin oscout reset v dd 0.1f + see clocks section v dd 0.1f 0.1f external reset circuit or configure unused i/o ports unused i/o 10nf 4.7k 10k by software as input with pull-up v dd detector (lvd) is used optional if low voltage
st7263 10/109 1.4 register & memory map as shown in figure 5 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 192 bytes of register location, up to 512 bytes of ram and up to 16k bytes of user program memory. the ram space includes up to 64 bytes for the stack from 0100h to 013fh. the highest address bytes contain the user reset and interrupt vectors. important : memory locations noted re- served must never be accessed. accessing a re- served area can have unpredictable effects on the device figure 5. memory map * program memory and ram sizes are product dependent (see table 1 device summary ) table 3. interrupt vector map * if the peripheral is present on the device (see table 1 device summary ) vector address description masked by remarks exit from halt mode fff0-fff1h fff2-fff3h fff4-fff5h fff6-fff7h fff8-fff9h fffa-fffbh fffc-fffdh fffe-ffffh usb interrupt vector sci interrupt vector* i 2 c interrupt vector* timer interrupt vector it1 to it8 interrupt vector usb end suspend mode interrupt vector trap (software) interrupt vector reset vector i- bit i- bit i- bit i- bit i- bit i- bit none none internal interrupt internal interrupt internal interrupt internal interrupt external interrupts internal interrupt cpu interrupt no no no no yes yes no yes 0000h interrupt & reset vectors hw registers 0040h 003fh (see table 4 ffefh fff0h ffffh (see table 3 on page 10) c000h bfffh f000h program memory* 512 bytes ram* 8k bytes 4k bytes e000h short addressing stack (64 bytes) 0100h 0040h 00ffh 013fh reserved 0240h 023fh ram (192 bytes) 16k bytes 256 bytes ram* short addressing stack (64 bytes) 0100h 0140h 023fh 0040h 00ffh 013fh 16-bit addressing ram ram (192 bytes) (256 bytes)
st7263 11/109 table 4. hardware register memory map address block register label register name reset status remarks 0000h 0001h padr paddr port a data register port a data direction register 00h 00h r/w r/w 0002h 0003h pbdr pbddr port b data register port b data direction register 00h 00h r/w r/w 0004h 0005h pcdr pcddr port c data register port c data direction register 1111 x000b 1111 x000b r/w r/w 0006h 0007h reserved (2 bytes) 0008h itifre interrupt register 00h r/w 0009h miscr miscellaneous register f0h r/w 000ah 000bh adc dr csr adc data register adc control status register 00h 00h read only r/w 000ch wdg cr watchdog control register 7fh r/w 000dh 0010h reserved (4 bytes) 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh tim cr2 cr1 sr ic1hr ic1lr oc1hr oc1lr chr clr achr aclr ic2hr ic2lr oc2hr oc2lr timer control register 2 timer control register 1 timer status register timer input capture high register 1 timer input capture low register 1 timer output compare high register 1 timer output compare low register 1 timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer input capture high register 2 timer input capture low register 2 timer output compare high register 2 timer output compare low register 2 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only r/w read only r/w read only read only r/w r/w 0020h 0021h 0022h 0023h 0024h sci 1) sr dr brr cr1 cr2 sci status register sci data register sci baud rate register sci control register 1 sci control register 2 c0h xxh 00xx xxxxb xxh 00h read only r/w r/w r/w r/w
st7263 12/109 note 1. if the peripheral is present on the device (see table 1 device summary ) 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h usb pidr dmar idr istr imr ctlr daddr ep0ra ep0rb ep1ra ep1rb ep2ra ep2rb usb pid register usb dma address register usb interrupt/dma register usb interrupt status register usb interrupt mask register usb control register usb device address register usb endpoint 0 register a usb endpoint 0 register b usb endpoint 1 register a usb endpoint 1 register b usb endpoint 2 register a usb endpoint 2 register b xxh xxh xxh 00h 00h xxxx 0110b 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0032h 0038h reserved (7 bytes) 0039h 003ah 003bh 003ch 003dh 003eh 003fh i 2 c 1) dr oar ccr sr2 sr1 cr i 2 c data register reserved i2c (7 bits) slave address register i 2 c clock control register i 2 c 2nd status register i 2 c 1st status register i 2 c control register 00h - 00h 00h 00h 00h 00h r/w r/w r/w read only read only r/w address block register label register name reset status remarks
st7263 13/109 1.5 eprom/otp program memory the program memory of the ST72T63 may be pro- grammed using the eprom programming boards available from stmicroelectronics (see table 26 ). 1.5.1 eprom erasure st72exxx eprom devices are erased by expo- sure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo current. it is recommended that the st72exxx devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm 2 is required to erase the st72exxx. the device will be erased in 15 to 30 minutes if such a uv lamp with a 12mw/cm 2 power rating is placed 1 inch from the device window without any interposed fil- ters.
st7263 14/109 2 central processing unit 2.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 2.3 cpu registers the 6 cpu registers shown in figure 1 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 6. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st7263 15/109 cpu registers (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. 70 111hinzc
st7263 16/109 cpu registers (contd) stack pointer (sp) read/write reset value: 01 3fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 7 ). since the stack is 64 bytes deep, the 10 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (sp5 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 7 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 7. stack manipulation example 15 8 00000001 70 0 0 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 013fh @ 0100h stack higher address = 013fh stack lower address = 0100h
st7263 17/109 3 clocks and reset 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu ) is de- rived from the external oscillator frequency (f osc ), which is divided by 3 (and by 2 or 4 for usb, de- pending on the external clock used). by setting the clkdiv bit in the miscellaneous register, a 12 mhz external clock can be used giv- ing an internal frequency of 4 mhz while maintain- ing a 6 mhz for usb (refer to figure 10 ). the internal clock signal (f cpu ) is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz or ceramic res- onator in the frequency range specified for f osc . the circuit shown in figure 9 is recommended when using a crystal, and table 5 recommended values for 24 mhz crystal resonator lists the rec- ommended capacitance. the crystal and associat- ed components should be mounted as close as possible to the input pins in order to minimize out- put distortion and start-up stabilisation time. table 5. recommended values for 24 mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). 3.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 8 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see sec- tion 6.5 control timing). figure 8. external clock source connections figure 9. crystal/ceramic resonator figure 10. clock block diagram r smax 20 w 25 w 70 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m w 1-10 m w 1-10 m w oscin oscout external clock nc oscin oscout c oscin c oscout r p %3 cpu and 8 or 4 mhz 6 mhz (usb) 24 or peripherals) %2 1 0 clkdiv %2 12 mhz crystal %2
st7263 18/109 3.2 reset the reset procedure is used to provide an orderly software start-up or to exit low power modes. three reset modes are provided: a low voltage (lvd) reset, a watchdog reset and an external re- set at the reset pin. a reset causes the reset vector to be fetched from addresses fffeh and ffffh in order to be loaded into the pc and with program execution starting from this point. an internal circuitry provides a 4096 cpu clock cy- cle delay from the time that the oscillator becomes active. 3.2.1 low voltage detector (lvd) low voltage reset circuitry generates a reset when v dd is: n below v it+ when v dd is rising, n below v it- when v dd is falling. during low voltage reset, the reset pin is held low, thus permitting the mcu to reset other devices. the low voltage detector can be disabled by set- ting the lvd bit of the miscellaneous register. 3.2.2 watchdog reset when a watchdog reset occurs, the reset pin is pulled low permitting the mcu to reset other devic- es in the same way as the low voltage reset ( fig- ure 11 ). 3.2.3 external reset the external reset is an active low input signal ap- plied to the reset pin of the mcu. as shown in figure 14 , the reset signal must stay low for a minimum of one and a half cpu clock cycles. an internal schmitt trigger at the reset pin is pro- vided to improve noise immunity. table 6. list of sections affected by reset, wait and halt (refer to 3.5 for wait and halt modes) section reset wait halt cpu clock running at 8 mhz x timer prescaler reset to zero x timer counter set to fffch x all timer enable bit set to 0 (disable) x data direction registers set to 0 (as inputs) x set stack pointer to 013fh x force internal address bus to restart vector fffeh,ffffh x set interrupt mask bit (i-bit, ccr) to 1 (interrupt disable) x set interrupt mask bit (i-bit, ccr) to 0 (interrupt enable) x x reset halt latch x reset wait latch x disable oscillator (for 4096 cycles) x x set timer clock to 0 x x watchdog counter reset x watchdog register reset x port data registers reset x other on-chip peripherals: registers reset x
st7263 19/109 figure 11. low voltage detector functional diagram figure 12. low voltage reset signal output note : hysteresis (v it+ -v it- ) = v hys figure 13. temporization timing diagram after an internal reset figure 14. reset timing diagram note: refer to electrical characteristics for values of t ddr , t oxov , v it+ , v it- and v hys low voltage v dd from watchdog reset reset internal detector reset reset v dd v it+ v it- v dd addresses $fffe temporization (4096 cpu clock cycles) v it+ v dd oscin f cpu ffff fffe pc reset watchdog reset t ddr t oxov 4096 cpu clock cycles delay
st7263 20/109 4 interrupts and power saving modes 4.1 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in table 7 interrupt mapping and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 15 . the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C the i bit of the cc register is set to prevent addi- tional interrupts. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 7 interrupt mapping for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt can not be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see table 7 interrupt mapping ). non maskable software interrupts this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 15 . interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific men- tioned interrupts allow the processor to leave the halt low power mode (refer to the exit from halt column in table 7 interrupt mapping ). external interrupts the pins iti/pak and itj/pbk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge oc- curs on this pin. conversely, pins itl/pan and itm/ pbn (l=3,4; m= 7,8; n=6,7) can generate an inter- rupt when a falling edge occurs on this pin. interrupt generation will occur if it is enabled with the itie bit (i=1 to 8) in the itrfre register and if the i bit of the ccr is reset. peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both. C the i bit of the cc register is cleared. C the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: C writing 0 to the corresponding bit in the status register or C an access to the status register while the flag is set followed by a read or write of an associated register. notes : 1. the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is exe- cuted. 2. all interrupts allow the processor to leave the wait low power mode. 3. exit from halt mode may only be triggered by an external interrupt on one of the iti ports (pa4-pa7 and pb4-pb7), an end suspend mode interrupt coming from usb peripheral, or a reset.
st7263 21/109 interrupts (contd) figure 15. interrupt processing flowchart table 7. interrupt mapping bit i set y n iret y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n n source block description register label priority order exit from halt vector address reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh usb end suspend mode istr yes fffah-fffbh 1 iti external interrupts itrfre fff8h-fff9h 2 timer timer peripheral interrupts timsr no fff6h-fff7h 3i 2 ci 2 c peripheral interrupts i2csr1 fff4h-fff5h i2csr2 4 sci sci peripheral interrupts scisr fff2h-fff3h 5 usb usb peripheral interrupts istr fff0h-fff1h
st7263 22/109 interrupts (contd) 4.1.1 interrupt register interrupts register (itrfre) address: 0008h read/write reset value: 0000 0000 (00h) bit 7:0 = itie (i=1 to 8) . interrupt enable control bits . if an itie bit is set, the corresponding interrupt is generated when C a rising edge occurs on the pin pa4/it1 or pa5/ it2 or pb4/it5 or pb5/it6 or C a falling edge occurs on the pin pa6/it3 or pa7/ it4 or pb6/it7 or pb7/it8 no interrupt is generated elsewhere. note : analog input must be disabled for interrupts coming from port b. 70 it8e it7e it6e it5e it4e it3e it2e it1e
st7263 23/109 4.2 power saving modes 4.2.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the st7. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. 4.2.2 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by ex- ecuting the halt instruction. the internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the condi- tion code register is cleared. thus, any of the ex- ternal interrupts (iti or usb end suspend mode), are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a reset. the oscillator is then turned on and a stabi- lization time is provided before releasing cpu op- eration. the stabilization time is 4096 cpu clock cycles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 16. halt mode flow chart n n external interrupt* reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
st7263 24/109 power saving modes (contd) 4.2.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0, to enable all interrupts. all other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 17 . figure 17. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 4096 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
st7263 25/109 5 on-chip peripherals 5.1 i/o ports 5.1.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C analog signal input (adc) C alternate signal input/output for the on-chip pe- ripherals. C external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put. 5.1.2 functional description each port is associated to 2 main registers: C data register (dr) C data direction register (ddr) each i/o pin may be programmed using the corre- sponding register bits in ddr register: bit x corre- sponding to pin x of the port. the same corre- spondence is used for the dr register. table 8. i/o pin functions input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. note 1 : all the inputs are triggered by a schmitt trigger. note 2 : when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. interrupt function when an i/o is configured in input with interrupt, an event on this i/o can generate an external in- terrupt request to the cpu. the interrupt sensitivi- ty is given independently according to the descrip- tion mentioned in the itrfre interrupt register. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, it masks the other ones. output mode the pin is configured in output mode by setting the corresponding ddr register bit (see table 7). in this mode, writing 0 or 1 to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pins state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. ddr mode 0 input 1 output
st7263 26/109 i/o ports (contd) analog alternate function when the pin is used as an adc input the i/o must be configured as input, floating. the analog multi- plexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings. 5.1.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr register and spe- cific feature of the i/o port such as adc input or true open drain.
st7263 27/109 i/o ports (contd) 5.1.4 port a table 9. port a0, a3, a4, a5, a6, a7 description figure 18. pa0, pa3, pa4, pa5, pa6, pa7 configuration port a i / o alternate function input* output signal condition pa0 with pull-up push-pull mco (main clock output) mco = 1 (miscr) pa3 with pull-up push-pull timer extclk cc1 =1 cc0 = 1 (timer cr2) pa4 with pull-up push-pull timer icap1 it1 schmitt triggered input it1e = 1 (itifre) pa5 with pull-up push-pull timer icap2 it2 schmitt triggered input it2e = 1 (itifre) pa6 with pull-up push-pull timer ocmp1 oc1e = 1 it3 schmitt triggered input it3e = 1 (itifre) pa7 with pull-up push-pull timer ocmp2 oc2e = 1 it4 schmitt triggered input it4e = 1 (itifre) *reset state dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus
st7263 28/109 i/o ports (contd) table 10. pa1, pa2 description figure 19. pa1, pa2 configuration port a i / o alternate function input* output signal condition pa1 without pull-up very high current open drain sda (i2c data) i2c enable pa2 without pull-up very high current open drain scl (i2c clock) i2c enable *reset state dr ddr latch latch dr sel ddr sel pa d alternate enable alternate enable alternate output n-buffer 1 0 1 0 cmos schmitt trigger v ss data bus
st7263 29/109 i/o ports (contd) 5.1.5 port b table 11. port b description figure 20. port b configuration port b i/o alternate function input* output signal condition pb0 without pull-up push-pull analog input (adc) ch[2:0] = 000 (adccsr) pb1 without pull-up push-pull analog input (adc) ch[2:0] = 001 (adccsr) pb2 without pull-up push-pull analog input (adc) ch[2:0]= 010 (adccsr) pb3 without pull-up push-pull analog input (adc) ch[2:0]= 011 (adccsr) pb4 without pull-up push-pull analog input (adc) ch[2:0]= 100 (adccsr) it5 schmitt triggered input it4e = 1 (itifre) pb5 without pull-up push-pull analog input (adc) ch[2:0]= 101 (adccsr) it6 schmitt triggered input it5e = 1 (itifre) pb6 without pull-up push-pull analog input (adc) ch[2:0]= 110 (adccsr) it7 schmitt triggered input it6e = 1 (itifre) pb7 without pull-up push-pull analog input (adc) ch[2:0]= 111 (adccsr) it8 schmitt triggered input it7e = 1 (itifre) *reset state dr ddr latch latch dr sel ddr sel v dd pa d analog switch analog enable (adc) alternate enable alternate enable digital enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 v ss data bus common analog rail v dd diodes
st7263 30/109 i/o ports (contd) 5.1.6 port c table 12. port c description figure 21. port c configuration port c i / o alternate function input* output signal condition pc0 with pull-up push-pull rdi (sci input) pc1 with pull-up push-pull tdo (sci output) sci enable pc2 with pull-up push-pull usboe (usb output ena- ble) usboe =1 (miscr) *reset state dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd data bus diodes
st7263 31/109 i/o ports (contd) 5.1.7 register description data registers (pxdr) port a data register (padr): 0000h port b data register (pbdr): 0002h port c data register (pcdr): 0004h read/write reset value port a: 0000 0000 (00h) reset value port b: 0000 0000 (00h) reset value port c: 1111 x000 (fxh) note: for port c, unused bits (7-3) are not acces- sible. bit 7:0 = d7-d0 data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken in account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital val- ue applied to the i/o pin (pin configured as input). data direction register (pxddr) port a data direction register (paddr): 0001h port b data direction register (pbddr): 0003h port c data direction register (pcddr): 0005h read/write reset value port a: 0000 0000 (00h) reset value port b: 0000 0000 (00h) reset value port c: 1111 x000 (fxh) note: for port c, unused bits (7-3) are not acces- sible bit 7:0 = dd7-dd0 data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode table 13. i/o ports register map 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 address (hex.) register label 765 4 3210 00 padr msb lsb 01 paddr msb lsb 02 pbdr msb lsb 03 pbddr msb lsb 04 pcdr msb lsb 05 pcddr msb lsb
st7263 32/109 5.2 miscellaneous register address: 0009h read/write reset value: 1111 0000 (f0h) bit 7:4 = reserved bit 3 = lvd low voltage detector. this bit is set by software and only cleared by hard- ware after a reset. 0: lvd enabled 1: lvd disabled bit 2 = clkdiv clock divider . this bit is set by software and only cleared by hard- ware after a reset. if this bit is set, it enables the use of a 12 mhz external oscillator (refer to figure 10 on page 17 ). 0: 24 mhz external oscillator 1: 12 mhz external oscillator. bit 1 = usboe usb enable. if this bit is set, the port pc2 outputs the usb out- put enable signal (at 1 when the st7 usb is transmitting data). unused bits 7-4 are set. bit 0 = mco main clock out selection this bit enables the mco alternate function on the pa0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) 70 ----lvdclkdivusboemco
st7263 33/109 5.3 watchdog timer (wdg) 5.3.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 5.3.2 main features n programmable timer (64 increments of 49152 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero figure 22. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 49152 t1 t2 t3 t4 t5
st7263 34/109 watchdog timer (contd) 5.3.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 14 . watchdog timing (fcpu = 8 mhz) ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 14. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 5.3.3.1 using halt mode with the wdg the halt instruction stops the oscillator. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 4096 cpu clocks. if a reset is generated, the wdg is disabled (reset state). recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input pull-up with interrupt before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. C for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 5.3.4 interrupts none. 5.3.5 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). cr register initial value wdg timeout period (ms) max ffh 393.216 min c0h 6.144 70 wdga t6 t5 t4 t3 t2 t1 t0
st7263 35/109 watchdog timer (contd) table 15. watchdog timer register map and reset values address (hex.) register label 765 4 3210 0c wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
st7263 36/109 5.4 16-bit timer 5.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 5.4.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 1 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 5.4.3 functional description 5.4.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 1 . the value in the counter register repeats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st7263 37/109 16-bit timer (contd) figure 23. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note)
st7263 38/109 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 5.4.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
st7263 39/109 16-bit timer (contd) figure 24. counter timing diagram, internal clock divided by 2 figure 25. counter timing diagram, internal clock divided by 4 figure 26. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st7263 40/109 16-bit timer (contd) 5.4.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: C select the timer clock (cc[1:0]) (see table 1 ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as a floating input). when an input capture occurs: C the icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 6 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr
st7263 41/109 16-bit timer (contd) figure 27. input capture block diagram figure 28. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
st7263 42/109 16-bit timer (contd) 5.4.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the ocie bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 1 ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 1 ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext
st7263 43/109 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 8 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 9 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 29. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1
st7263 44/109 16-bit timer (contd) figure 30. output compare timing diagram, f timer =f cpu /2 figure 31. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st7263 45/109 16-bit timer (contd) 5.4.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 1 ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 10 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st7263 46/109 16-bit timer (contd) figure 32. one pulse mode timing example figure 33. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2
st7263 47/109 16-bit timer (contd) 5.4.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 1 ). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 11 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st7263 48/109 16-bit timer (contd) 5.4.4 low power modes 5.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 5.4.6 summary of timer modes 1) see note 4 in section 0.1.3.5 one pulse mode 2) see note 5 in section 0.1.3.5 one pulse mode 3) see note 4 in section 0.1.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no
st7263 49/109 16-bit timer (contd) 5.4.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
st7263 50/109 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 16. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11
st7263 51/109 16-bit timer (contd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st7263 52/109 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st7263 53/109 16-bit timer (contd) table 17. 16-bit timer register map and reset values address (hex.) register label 76543210 11 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 12 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 13 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 0 0 0 0 0 0 14 ic1hr reset value msb lsb 15 ic1lr reset value msb lsb 16 oc1hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 17 oc1lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 18 chr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 19 clr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1a achr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 1b aclr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1c ic2hr reset value msb lsb 1d ic2lr reset value msb lsb 1e oc2hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 1f oc2lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0
st7263 54/109 5.5 serial communications interface (sci) 5.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. 5.5.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n independently programmable transmit and receive baud rates up to 250k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: C overrun error C noise error C frame error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected 5.5.3 general description the interface is externally connected to another device by two pins (see figure 1): C tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is complete.
st7263 55/109 serial communications interface (contd) figure 34. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe - cr2 sbk rwu re te ilie rie tcie tie sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 baud rate generator
st7263 56/109 serial communications interface (contd) 5.5.4 functional description the block diagram of the serial control interface, is shown in figure 1. it contains 4 dedicated regis- ters: C two control registers (cr1 & cr2) C a status register (sr) C a baud rate register (brr) refer to the register descriptions in section 0.1.7 for the definitions of each bit. 5.5.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 1). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 35. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame
st7263 57/109 serial communications interface (contd) 5.5.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 1). procedure C select the m bit to define the word length. C select the desired baud rate using the brr reg- ister. C set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. C access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. the following software sequence is always to clear the tdre bit: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates that: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the cc register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the cc register. the following software sequence is always to clear the tc bit: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 2). as long as the sbk bit is set, the sci sends break frames to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, i.e. before writing the next byte in the dr.
st7263 58/109 serial communications interface (contd) 5.5.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the dr register consists of a buffer (rdr) between the internal bus and the received shift register (see figure 1). procedure C select the m bit to define the word length. C select the desired baud rate using the brr reg- ister. C set the re bit to enable the receiverto begin searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the i bit is cleared in the cc register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the cc register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the i bit is cleared in the cc register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation.
st7263 59/109 serial communications interface (contd) 5.5.4.4 baud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all these bits are in the brr register. example: if f cpu is 8 mhz and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 bauds. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 5.5.4.5 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. the receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. the receiver wakes-up by address mark detec- tion when it received a 1 as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to re- ceive this word normally and to use it as an ad- dress word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu
st7263 60/109 serial communications interface (contd) 5.5.5 low power modes 5.5.6 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no
st7263 61/109 serial communications interface (contd) 5.5.7 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if tie =1 in the cr2 register. it is cleared by a software sequence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when an idle line is de- tected. an interrupt is generated if ilie=1 in the cr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set the rdr register content will not be lost but the shift register will be overwrit- ten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr regis- ter). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = reserved, forced by hardware to 0. 70 tdre tc rdrf idle or nf fe 0
st7263 62/109 serial communications interface (contd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = reserved, forced by hardware to 0. bit 4 = m word length. this bit determines the data length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bits 2:0 = reserved, forced by hardware to 0. control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the sr register. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to 1 and then to 0, the transmitter will send a br eak word at the end of the current word. 70 r8 t8 0 m wake 0 0 0 70 tie tcie rie ilie te re rwu sbk
st7263 63/109 serial communications interface (contd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 1). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 1). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits, define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1
st7263 64/109 serial communications interface (contd) table 18. sci register map and reset values address (hex.) register label 76543210 20 sr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 0 0 21 dr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 22 brr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 23 cr1 reset value r8 x t8 x 0 0 m x wake x 0 0 0 0 0 0 24 cr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0
st7263 65/109 5.6 usb interface (usb) 5.6.1 introduction the usb interface implements a low-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and dma. no external components are needed apart from the external pull-up on usbdm for low speed recognition by the usb host. the use of dma architecture allows the endpoint definition to be completely flexible. endpoints can be config- ured by software as in or out. 5.6.2 main features n usb specification version 1.1 compliant n supports low-speed usb protocol n two or three endpoints (including default one) depending on the device (see device feature list and register map) n crc generation/checking, nrzi encoding/ decoding and bit-stuffing n usb suspend/resume operations n dma data transfers n on-chip 3.3v regulator n on-chip usb transceiver 5.6.3 functional description the block diagram in figure 1 , gives an overview of the usb interface hardware. for general information on the usb, refer to the universal serial bus specifications document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. dma when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place, using dma. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 36. usb block diagram cpu memory transceiver 3.3v voltage regulator sie endpoint dma interrupt address, and interrupts usbdm usbdp usbvcc 6 mhz registers registers data buses usbgnd
st7263 66/109 usb interface (contd) 5.6.4 register description dma address register (dmar) read / write reset value: undefined bits 7:0= da[15:8] dma address bits 15-8. software must write the start address of the dma memory area whose most significant bits are given by da15-da6. the remaining 6 address bits are set by hardware. see the description of the idr register and figure 2 . interrupt/dma register (idr) read / write reset value: xxxx 0000 (x0h) bits 7:6 = da[7:6] dma address bits 7-6. software must reset these bits. see the descrip- tion of the dmar register and figure 2 . bits 5:4 = ep[1:0] endpoint number (read-only). these bits identify the endpoint which required at- tention. 00: endpoint 0 01: endpoint 1 10: endpoint 2 when a ctr interrupt occurs (see register istr) the software should read the ep bits to identify the endpoint which has sent or received a packet. bits 3:0 = cnt[3:0] byte count (read only). this field shows how many data bytes have been received during the last data reception. note: not valid for data transmission. figure 37. dma buffers 70 da15 da14 da13 da12 da11 da10 da9 da8 70 da7 da6 ep1 ep0 cnt3 cnt2 cnt1 cnt0 endpoint 0 rx endpoint 0 tx endpoint 2 rx endpoint 1 tx 000000 000111 001000 001111 010000 010111 011000 011111 da15-6,000000 endpoint 1 rx endpoint 2 tx 100000 100111 101000 101111
st7263 67/109 usb interface (contd) pid register (pidr) read only reset value: xx00 0000 (x0h) bits 7:6 = tp[3:2] token pid bits 3 & 2 . usb token pids are encoded in four bits. tp[3:2] correspond to the variable token pid bits 3 & 2. note: pid bits 1 & 0 have a fixed value of 01. when a ctr interrupt occurs (see register istr) the software should read the tp3 and tp2 bits to retrieve the pid name of the token received. the usb standard defines tp bits as: bits 5:3 reserved. forced by hardware to 0. bit 2 = rx_sez received single-ended zero this bit indicates the status of the rx_sez trans- ceiver output. 0: no se0 (single-ended zero) state 1: usb lines are in se0 (single-ended zero) state bit 1 = rxd received data 0: no k-state 1: usb lines are in k-state this bit indicates the status of the rxd transceiver output (differential receiver output). note: if the environment is noisy, the rx_sez and rxd bits can be used to secure the application. by interpreting the status, software can distinguish a valid end suspend event from a spurious wake-up due to noise on the external usb line. a valid end suspend is followed by a resume or reset se- quence. a resume is indicated by rxd=1, a re- set is indicated by rx_sez=1. bit 0 = reserved. forced by hardware to 0. interrupt status register (istr) read / write reset value: 0000 0000 (00h) when an interrupt occurs these bits are set by hardware. software must read them to determine the interrupt type and clear them after servicing. note: these bits cannot be set by software. bit 7 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb bus. the suspend request check is active immedi- ately after each usb reset event and its disabled by hardware when suspend mode is forced (fsusp bit of ctlr register) until the end of resume sequence. bit 6 = dovr dma over/underrun . this bit is set by hardware if the st7 processor cant answer a dma request in time. 0: no over/underrun detected 1: over/underrun detected bit 5 = ctr correct transfer. this bit is set by hardware when a correct transfer operation is per- formed. the type of transfer can be determined by looking at bits tp3-tp2 in register pidr. the end- point on which the transfer was made is identified by bits ep1-ep0 in register idr. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 4 = err error. this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing or nonstandard framing error detected 70 tp3tp2000 rx_ sez rxd 0 tp3 tp2 pid name 00 out 10 in 1 1 setup 70 susp dovr ctr err iovr esusp reset sof
st7263 68/109 usb interface (contd) bit 3 = iovr interrupt overrun. this bit is set when hardware tries to set err, or sof before they have been cleared by software. 0: no overrun detected 1: overrun detected bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0ra, ep0rb, ep1ra, ep1rb, ep2ra and ep2rb registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardware when a low-speed sof indication (keep-alive strobe) is seen on the usb bus. it is also issued at the end of a resume se- quence. 0: no sof signal detected 1: sof signal detected note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and , xor.. interrupt mask register (imr) read / write reset value: 0000 0000 (00h) bits 7:0 = these bits are mask bits for all interrupt condition bits included in the istr. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the corresponding bit description in istr. control register (ctlr) read / write reset value: 0000 0110 (06h) bits 7:4 = reserved. forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be halted allowing at least 600 ns before issuing the halt instruction. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset state until software clears this bit, at which point a usb-reset in- terrupt will be generated if enabled. 70 sus pm dov rm ctr m err m iovr m esu spm res etm sof m 70 0 0 0 0 resume pdwn fsusp fres
st7263 69/109 usb interface (contd) device address register (daddr) read / write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received from the usb bus or forced through bit fres in the ctlr register. endpoint n register a (epnra) read / write reset value: 0000 xxxx (0xh) these registers ( ep0ra , ep1ra and ep2ra ) are used for controlling data transmission. they are also reset by the usb bus reset. note : endpoint 2 and the ep2ra register are not available on some devices (see device feature list and register map). bit 7 = st_out status out. this bit is set by software to indicate that a status out packet is expected: in this case, all nonzero out data transfers on the endpoint are stalled instead of being acked. when st_out is reset, out transactions can have any number of bytes, as needed. bit 6 = dtog_tx data toggle, for transmission transfers. it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware at the re- ception of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx (see epnrb) are normally updated by hardware, at the receipt of a relevant pid. they can be also written by software. bits 5:4 = stat_tx[1:0] status bits, for transmis- sion transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) related to a in or setup transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. bits 3:0 = tbc[3:0] transmit byte count for end- point n. before transmission, after filling the transmit buff- er, software must write in the tbc field the trans- mit packet size expressed in bytes (in the range 0- 8). 70 0 add6 add5 add4 add3 add2 add1 add0 70 st_ out dtog _tx stat _tx1 stat _tx0 tbc 3 tbc 2 tbc 1 tbc 0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission.
st7263 70/109 usb interface (contd) endpoint n register b (epnrb) read / write reset value: 0000 xxxx (0xh) these registers ( ep1rb and ep2rb ) are used for controlling data reception on endpoints 1 and 2. they are also reset by the usb bus reset. note : endpoint 2 and the ep2rb register are not available on some devices (see device feature list and register map). bit 7 = ctrl control. this bit should be 0. note: if this bit is 1, the endpoint is a control end- point. (endpoint 0 is always a control endpoint, but it is possible to have more than one control end- point). bit 6 = dtog_rx data toggle, for reception trans- fers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by hardware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. bits 5:4 = stat_rx [1:0] status bits, for reception transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) related to an out or set- up transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. bits 3:0 = ea[3:0] endpoint address . software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. usually ep1rb contains 0001 and ep2rb contains 0010. endpoint 0 register b (ep0rb) read / write reset value: 1000 0000 (80h) this register is used for controlling data reception on endpoint 0. it is also reset by the usb bus re- set. bit 7 = forced by hardware to 1. bits 6:4 = refer to the epnrb register for a de- scription of these bits. bits 3:0 = forced by hardware to 0. 70 ctrl dtog _rx stat _rx1 stat _rx0 ea3 ea2 ea1 ea0 stat_rx1 stat_rx0 meaning 00 disabled : reception transfers cannot be exe- cuted. 01 stall: the endpoint is stalled and all reception requests result in a stall handshake. 10 nak : the endpoint is na- ked and all reception re- quests result in a nak handshake. 11 valid : this endpoint is enabled for reception. 70 1 dtog rx stat rx1 stat rx0 0000 stat_rx1 stat_rx0 meaning
st7263 71/109 usb interface (contd) 5.6.5 programming considerations the interaction between the usb interface and the application program is described below. apart from system reset, action is always initiated by the usb interface, driven by one of the usb events associated with the interrupt status register (is- tr) bits. 5.6.5.1 initializing the registers at system reset, the software must initialize all reg- isters to enable the usb interface to properly gen- erate interrupts and dma requests. 1. initialize the dmar, idr, and imr registers (choice of enabled interrupts, address of dma buffers). refer the paragraph titled initializing the dma buffers. 2. initialize the ep0ra and ep0rb registers to enable accesses to address 0 and endpoint 0 to support usb enumeration. refer to the para- graph titled endpoint initialization. 3. when addresses are received through this channel, update the content of the daddr. 4. if needed, write the endpoint numbers in the ea fields in the ep1rb and ep2rb register. 5.6.5.2 initializing dma buffers the dma buffers are a contiguous zone of memo- ry whose maximum size is 48 bytes. they can be placed anywhere in the memory space to enable the reception of messages. the 10 most signifi- cant bits of the start of this memory area are spec- ified by bits da15-da6 in registers dmar and idr, the remaining bits are 0. the memory map is shown in figure 2 . each buffer is filled starting from the bottom (last 3 address bits=000) up. 5.6.5.3 endpoint initialization to be ready to receive: set stat_rx to valid (11b) in ep0rb to enable reception. to be ready to transmit: 1. write the data in the dma transmit buffer. 2. in register epnra, specify the number of bytes to be transmitted in the tbc field 3. enable the endpoint by setting the stat_tx bits to valid (11b) in epnra. note: once transmission and/or reception are en- abled, registers epnra and/or epnrb (respec- tively) must not be modified by software, as the hardware can change their value on the fly. when the operation is completed, they can be ac- cessed again to enable a new operation. 5.6.5.4 interrupt handling start of frame (sof) the interrupt service routine may monitor the sof events for a 1 ms synchronization event to the usb bus. this interrupt is generated at the end of a resume sequence and can also be used to de- tect this event. usb reset (r eset) when this event occurs, the daddr register is re- set, and communication is disabled in all endpoint registers (the usb interface will not respond to any packet). software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. to do this, set the stat_rx bits in the ep0rb register to valid. suspend (susp) the cpu is warned about the lack of bus activity for more than 3 ms, which is a suspend request. the software should set the usb interface to sus- pend mode and execute an st7 halt instruction to meet the usb-specified power constraints. end suspend (esusp) the cpu is alerted by activity on the usb, which causes an esusp interrupt. the st7 automatical- ly terminates halt mode. correct transfer (ctr) 1. when this event occurs, the hardware automat- ically sets the stat_tx or stat_rx to nak. note: every valid endpoint is naked until soft- ware clears the ctr bit in the istr register, independently of the endpoint number addressed by the transfer which generated the ctr interrupt. note: if the event triggering the ctr interrupt is a setup transaction, both stat_tx and stat_rx are set to nak. 2. read the pidr to obtain the token and the idr to get the endpoint number related to the last transfer. note: when a ctr interrupt occurs, the tp3- tp2 bits in the pidr register and ep1-ep0 bits in the idr register stay unchanged until the ctr bit in the istr register is cleared. 3. clear the ctr bit in the istr register.
st7263 72/109 usb interface (contd) table 19. usb register map and reset values address (hex.) register name 7 6 5 4 3210 25 pidr reset value tp3 x tp2 x 0 0 0 0 0 0 rx_sez 0 rxd 0 0 0 26 dmar reset value da15 x da14 x da13 x da12 x da11 x da10 x da9 x da8 x 27 idr reset value da7 x da6 x ep1 x ep0 x cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 istr reset value susp 0 dovr 0 ctr 0 err 0 iovr 0 esusp 0 reset 0 sof 0 29 imr reset value suspm 0 dovrm 0 ctrm 0 errm 0 iovrm 0 esuspm 0 resetm 0 sofm 0 2a ctlr reset value 0 0 0 0 0 0 0 0 resume 0 pdwn 1 fsusp 1 fres 0 2b daddr reset value 0 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2c ep0ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2d ep0rb reset value 1 1 dtog_rx 0 stat_rx1 0 stat_rx0 0 0 0 0 0 0 0 0 0 2e ep1ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2f ep1rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x 30 ep2ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 31 ep2rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x
st7263 73/109 5.7 i2c bus interface (i2c) 5.7.1 introduction the i2c bus interface serves as an interface be- tween the microcontroller and the serial i2c bus. it provides both multimaster and slave functions, and controls all i2c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i2c mode (400 khz). 5.7.2 main features n parallel-bus/i2c protocol converter n multi-master capability n 7-bit addressing n transmitter/receiver flag n end-of-byte transmission flag n transfer problem detection i2c master features: n clock generation n i2c bus busy flag n arbitration lost flag n end of byte transmission flag n transmitter/receiver flag n start bit detection flag n start and stop generation i2c slave features: n stop bit detection n i2c bus busy flag n detection of misplaced start or stop condition n programmable i2c address detection n transfer problem detection n end-of-byte transmission flag n transmitter/receiver flag 5.7.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i2c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i2c bus and a fast i2c bus. this selection is made by soft- ware. mode selection the interface can operate in the four following modes: C slave transmitter/receiver C master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, this allows multi-master capa- bility. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condi- tion is the address byte; it is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 1 . figure 38. i2c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b
st7263 74/109 i2c bus interface (contd) the acknowledge function may be enabled and disabled by software. the i2c interface address and/or general call ad- dress can be selected by software. the speed of the i2c interface may be selected be- tween standard (0-100 khz) and fast i2c (100- 400 khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i2c bus mode. when the i2c cell is enabled, the sda and scl ports must be configured as floating open-drain output or floating input. in this case, the value of the external pull-up resistor used depends on the application. when the i2c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 39. i2c interface block diagram data register (dr) data shift register comparator own address register (oar) clock control register (ccr) status register 1 (sr1) control register (cr) sdai scli control logic status register 2 (sr2) interrupt clock control data control scl sda
st7263 75/109 i2c bus interface (contd) 5.7.4 functional description refer to the cr, sr1 and sr2 registers in section 0.1.7 . for the bit definitions. by default the i2c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. 5.7.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: C an acknowledge pulse is generated if the ack bit is set. C evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 3 transfer sequencing ev1). next, software must read the dr register to deter- mine from the least significant bit if the slave must enter receiver or transmitter mode. slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: C an acknowledge pulse is generated if the ack bit is set C evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 3 transfer sequenc- ing ev2). slave transmitter following the address reception and after the sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 3 transfer sequencing ev3). when the acknowledge pulse is received: C the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: C evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 3 transfer sequencing ev4). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set with an interrupt if the ite bit is set. if it is a stop condition, then the interface dis- cards the data, released the lines and waits for another start condition. if it is a start condition, then the interface dis- cards the data and waits for the next slave ad- dress on the bus. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note : in both cases, the scl line is not held low; however, the sda line can remain low due to pos- sible 0 bits transmitted last. it is then necessary to release both lines by software. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte.
st7263 76/109 i2c bus interface (contd) 5.7.4.2 master mode to switch from default slave mode to master mode, a start condition generation is needed. start condition and transmit slave address setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: C the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address byte, holding the scl line low (see figure 3 transfer sequencing ev5). then the slave address byte is sent to the sda line via the internal shift register. after completion of this transfer (and acknowledge from the slave if the ack bit is set): C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 3 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. master receiver following the address transmission and after the sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: C an acknowledge pulse is generated if if the ack bit is set C evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 3 transfer sequenc- ing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface returns automatically to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 3 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: C evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if the ite bit is set. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. C arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible 0 bits transmitted last. it is then neces- sary to release both lines by software.
st7263 77/109 i2c bus interface (contd) figure 40. transfer sequencing legend: s=start, p=stop, a=acknowledge, na=non-acknowledge evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading the sr1 register. ev2: evf=1, btf=1, cleared by reading the sr1 register followed by reading the dr register. ev3: evf=1, btf=1, cleared by reading the sr1 register followed by writing the dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by reading the sr1 register. the btf is cleared by releasing the lines (stop=1, stop=0) or by writing the dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading the sr2 register. ev5: evf=1, sb=1, cleared by reading the sr1 register followed by writing the dr register. ev6: evf=1, cleared by reading the sr1 register followed by writing the cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading the sr1 register followed by reading the dr register. ev8: evf=1, btf=1, cleared by reading the sr1 register followed by writing the dr register. sl ave r ece i ver slave transmitter master receiver master transmitter s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8
st7263 78/109 i2c bus interface (contd) 5.7.5 low power modes 5.7.6 interrupts figure 41. event flags and interrupt generation the i2c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). mode description wait no effect on i2c interface. i2c interrupts exit from wait mode. halt i2c registers are frozen. in halt mode, the i2c interface is inactive and does not acknowledge data on the bus. the i2c interface resumes operation when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt end of byte transfer event btf ite yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register.
st7263 79/109 i2c bus interface (contd) 5.7.7 register description i2c control register (cr) read / write reset value: 0000 0000 (00h) bits 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes : C when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 C when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. C to enable the i2c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). C in master mode: 0: no start generation 1: repeated start generation C in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). C in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. C in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 4 for the relationship between the events and the interrupt. scl is held low when the sb, btf or adsl flags or an ev6 event (see figure 3 ) is detected. 70 0 0 pe engc start ack stop ite
st7263 80/109 i2c bus interface (contd) i2c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 3 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: C btf=1 (byte received or transmitted) C adsl=1 (address matched in slave mode while ack=1) C sb=1 (start condition generated in master mode) C af=1 (no acknowledge received after byte transmission) C stopf=1 (stop condition detected in slave mode) C arlo=1 (arbitration lost in master mode) C berr=1 (bus error, misplaced start or stop condition detected) C address byte successfully transmitted in mas- ter mode. bit 6 = reserved. forced to 0 by hardware. bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still updat- ed when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). C following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 3 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. C following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated 70 evf 0 tra busy btf adsl m/sl sb
st7263 81/109 i2c bus interface (contd) i2c status register 2 (sr2) read only reset value: 0000 0000 (00h) bits 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal
st7263 82/109 i2c bus interface (contd) i2c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i2c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i2c mode 1: fast i2c mode bits 6:0 = cc6-cc0 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i2c mode. they are not cleared when the interface is disabled (pe=0). C standard mode (fm/sm=0): f scl <= 100khz f scl = f cpu /(2x([cc6..cc0]+2)) C fast mode (fm/sm=1): f scl > 100khz f scl = f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i2c data register ( dr) read / write reset value: 0000 0000 (00h) bits 7:0 = d7-d0 8-bit data register. these bits contains the byte to be received or transmitted on the bus. C transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. C receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the next data bytes are received one by one after reading the dr register. i2c own address register (oar) read / write reset value: 0000 0000 (00h) bits 7:1 = add7-add1 interface address . these bits define the i2c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is dont care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 70 add7 add6 add5 add4 add3 add2 add1 add0
st7263 83/109 table 20. i 2 c register map address (hex.) register name 765 4 3210 39 dr dr7 .. dr0 3b oar add7 .. add0 3c ccr fm/sm cc6 .. cc0 3d sr2 af stopf arlo berr gcal 3e sr1 evf tra busy btf adsl m/sl sb 3f cr pe engc start ack stop ite
st7263 84/109 5.8 8-bit a/d converter (adc) 5.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 5.8.2 main features n 8-bit conversion n up to 8 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 42 . figure 42. adc block diagram sample analog mux ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 (control status register) csr (data register) dr & hold f cpu analog to digital converter coco 0ch0 ch1 ch2 - -adon ad7 ad4 ad0 ad1 ad2 ad3 ad6 ad5
st7263 85/109 8-bit a/d converter (adc) (contd) 5.8.3 functional description the high level reference voltage v dda must be connected externally to the v dd pin. the low level reference voltage v ssa must be connected exter- nally to the v ss pin. in some devices (refer to de- vice pin out description) high and low level refer- ence voltages are internally connected to the v dd and v ss pins. conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 43. recommended ext. connections characteristics: the conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. if input voltage is greater than or equal to v dd (voltage reference high) then results = ffh (full scale) without overflow indication. if input voltage v ss (voltage reference low) then the results = 00h. the conversion time is 64 cpu clock cycles in- cluding a sampling time of 31.5 cpu clock cycles. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. the a/d converter is linear and the digital result of the conversion is given by the formula: where reference voltage is v dd - v ss . the accuracy of the conversion is described in the electrical characteristics section. procedure: refer to the csr and dr register description sec- tion for the bit definitions. each analog input pin must be configured as input, no pull-up, no interrupt. refer to the i/o ports chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch2 to ch0 bits to assign the ana- log channel to convert. refer to table 21 channel selection . C set the adon bit. then the a/d converter is enabled after a stabilization time (typically 30 s). it then performs a continuous conversion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register. a write to the csr register aborts the current con- version, resets the coco bit and starts a new conversion. 5.8.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed. 5.8.5 interrupts none. st7 px.x/ainx v dda v ssa v dd 0.1f r ain v ain digital result = 255 x input voltage reference voltage mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilisation time before accurate conversions can be performed.
st7263 86/109 8-bit a/d converter (adc) (contd) 5.8.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete. 1: conversion can be read from the dr register. bit 6 = reserved . must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off. 1: a/d converter is switched on. note : a typical 30 s delay time is necessary for the adc to stabilize when the adon bit is set. bit 4 = reserved . forced by hardware to 0. bit 3 = reserved . must always be cleared. bits 2:0: ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 21. channel selection * important note: the number of pins and the channel selection vary according to the device. refer to the device pinout). data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = ad[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. reading this register resets the coco flag. 70 coco - adon 0 - ch2 ch1 ch0 pin* ch2 ch1 ch0 ain0 000 ain1 001 ain2 010 ain3 011 ain4 100 ain5 101 ain6 110 ain7 111 70 ad7ad6ad5ad4ad3ad2ad1ad0
st7263 87/109 6 instruction set 6.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 22. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st7263 88/109 st7 addressing modes (contd) 6.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 6.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 6.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 6.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 6.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st7263 89/109 st7 addressing modes (contd) 6.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 23. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 6.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative
st7263 90/109 6.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf
st7263 91/109 instruction groups (contd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st7263 92/109 instruction groups (contd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z
st7263 93/109 7 electrical characteristics 7.1 absolute maximum ratings devices of the st72 family contain circuitry to pro- tect the inputs against damage due to high static voltage or electric fields. nevertheless, it is recom- mended that normal precautions be observed in order to avoid subjecting this high-impedance cir- cuit to voltages above those quoted in the abso- lute maximum ratings. for proper operation, it is recommended that the input voltage v in be con- strained within the range: (v ss - 0.3v) v in (v dd + 0.3v) to enhance reliability of operation, it is recom- mended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as v ss or v dd . it is also recommended to connect v dda and v dd together on application. (same remark for v ssa and v ss ). all the voltage in the following tables are refer- enced to v ss . stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. functional operation of the device at these conditions is not implied. exposure to maxi- mum rating conditions for extended periods may affect device reliability. table 24. absolute maximum ratings (voltage referenced to v ss ) symbol ratings value unit v dd recommended supply voltage - 0.3 to +6.0 v v dda analog reference voltage - 0.3 to +6.0 v |v dda - v dd | max. variations on power line 50 mv |v ssa - v ss | max. variations on ground line 50 mv i vdd - i vss total current into v dd /v ss 80/80 ma v in input voltage v ss - 0.3 to v dd + 0.3 v v out output voltage v ss - 0.3 to v dd + 0.3 v t a ambient temperature range t l to t h 0 to + 70 c t stg storage temperature range -65 to +150 c t j junction temperature 150 c pd power dissipation 350 mw esd esd susceptibility 2000 v
st7263 94/109 7.2 thermal characteristics the average chip-junction temperature, t j , in de- grees celsius, may be calculated using the follow- ing equation: t j = t a + (p d x q j a ) (1)* where: C t a is the ambient temperature in c, C q j a is the package junction-to-ambient thermal resistance, in c/w, C p d is the sum of p int and p i/o , C p int is the product of i dd and v dd , expressed in watts. this is the chip internal power C p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o

st7263 95/109 7.3 operating conditions general operating conditions (t a = 0 to +70c unless otherwise specified) note 1: usb 1.1 specifies that the power supply must be between 4.00 and 5.25 volts. the usb cell is therefore guaranteed only in that range. symbol parameter conditions min max unit v dd supply voltage 1) f cpu = 4 mhz ; usb not guaranteed 3.00 4.00 v f cpu = 8 mhz ; usb not guaranteed v it+ 4.00 v f cpu = 8 mhz or 4 mhz usb guaranteed 4.0 5.25 f cpu = 8 mhz or 4 mhz usb not guaranteed 5.25 5.50 f osc external clock frequency 12 24 mhz
st7263 96/109 7.4 power consumption (t a = 0 to +70c unless otherwise specified) note 1: all peripherals running. note 2: oscillator, 16-bit timer (free running counter) and watchdog running. all others peripherals (including eprom/ram memories) disabled. note 3: cpu in halt mode, usb transceiver disabled, low voltage reset function enabled. note 4: low voltage reset function enabled. cpu in halt mode. usb in suspend mode. external pull-up (1.5kohms to usbvcc) and pull-down (15kohms to v ssa ) connected on drivers. note 5: v dd = 5.5 v except in usb suspend mode where v dd = 5.25 v general symbol parameter conditions min typ. max unit v dd operating supply voltage run & wait mode f osc = 24 mhz f cpu = 8 mhz 4 5 5.5 v v dda analog reference voltage 4 5 5.5 v i dd cpu run mode (see note 1) i/o in input mode f cpu = 8 mhz, t a = 20 c (for v dd : see note 5) 14 20 ma cpu wait mode (see note 2) 8 12 ma cpu halt mode (see note 3) 100 m a usb suspend mode (see note 4) 350 450 m a
st7263 97/109 7.5 i/o port characteristics (t a = 0 to +70c unless otherwise specified) all voltages are referred to v ss unless otherwise specified . note 1: guaranteed by design, not tested in production. note 2: data based on characterization results, not tested in production. standard i/o port pins symbol parameter conditions min typ max unit v ol output low level voltage port a1, port a2 (high current open drain) i ol = -25ma v dd =5v - - 1.5 v output low level voltage port a0, port a(3:7), port c(0:2), push pull i ol = -1.6ma v dd =5v - - 0.4 v output low level voltage port b (0:7), push pull i ol = -10ma v dd =5v - - 1.3 v v oh output high level voltage port a0, port a(3:7), port c(0:2) push pull i oh = 1.6ma v dd -0.8 - - v v oh output high level voltage port b (0:7) push pull i oh = 10ma v dd -1.3 - - v v ih input high level voltage pa(0:7),pb(0:7),pc(0:2),reset leading edge 0.7xv dd v dd v v il input low voltage pa(0-7), pb(0-7), pc(0-2), reset trailing edge v ss 0.3xv dd v r pu pull-up resistor v dd = 5v 80 100 120 k w cio i/o pin capacitance 1) 5pf t f(io)out output high to low level fall time all i/o ports cl=50pf between 10% and 90% 25 2) ns t r(io)out output low to high level rise time i/o ports in push pull mode 25 2) ns t r(io)out external interrupt pulse time 1) 1t cpu
st7263 98/109 7.6 low voltage detector (lvd) characteristics 7.7 control timing characteristics (operating conditions t a = 0 to +70c unless otherwise specified) note 1: the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. c low voltage reset electrical specifications symbol parameter conditions min typ max unit v it+ low voltage reset threshold v dd rising v dd max. variation 50mv/ m s 3.6 3.75 4.0 v v it- low voltage reset threshold v dd falling v dd max. variation 50mv/ m s 3.2 3.5 3.7 v v hys hysteresis (v it+ - v it- ) 200 250 mv control timings symbol parameter conditions value unit min typ. max f osc oscillator frequency 24 mhz f cpu operating frequency 8 mhz t rl external reset input pulse width 1.5 t cpu t porl internal power reset duration 4096 t cpu t dogl watchdog & low voltage reset output pulse width 200 ns t dog watchdog time-out f cpu = 8mhz 49152 6 3145728 384 t cpu ms t oxov crystal oscillator start-up time 50 ms t ddr power up rise time from v dd = 0 to 4v 100 ms
st7263 99/109 7.8 communication interface characteristics the values given in the specifications of dedicated functions are generally not applicable for chips. therefore, only the limits listed below are valid for the product. t = 0... +70c, v dd - v ss = 5 v unless otherwise specified . 7.8.1 usb - universal bus interface (operating conditions t a = 0 to +70c, v dd = 4.0 to 5.25v unless otherwise specified) note 1: rl is the load connected on the usb drivers. note 2: all the voltages are measured from the local ground potential. usb dc electrical characteristics parameter symbol conditions min. max. unit input levels: differential input sensitivity vdi i(d+, d-) 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 v single ended receiver threshold vse 0.8 2.0 v output levels static output low vol rl of 1.5k ohms to 3.6v 0.3 v static output high voh rl of 15k ohm to v ss 2.8 3.6 v usbvcc: voltage level usbv v dd =5v 3.00 3.60 v
st7263 100/109 communication interface characteristics (contd) figure 44. usb: data signal rise and fall time note1: measured from 10% to 90% of the data signal. for more detailed informations, please refer to chapter 7 (elec- trical) of the usb specification (version 1.1). usb: low speed electrical characteristics parameter symbol conditions min max unit driver characteristics: rise time tr note 1,cl=50 pf 75 ns note 1, cl=600 pf 300 ns fall time tf note 1, cl=50 pf 75 ns note 1, cl=600 pf 300 ns rise/ fall time matching trfm tr/tf 80 120 % output signal crossover voltage vcrs 1.3 2.0 v differential data lines v ss tf tr crossover points vcrs
st7263 101/109 communication interface characteristics (contd) 7.8.2 i 2 c - inter ic control interface 1) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl 2) the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf i 2 c/ddc-bus timings parameter standard i 2 c fast i 2 c symbol unit min max min max bus free time between a stop and start con- dition 4.7 1.3 t buf ms hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 t hd:sta m s low period of the scl clock 4.7 1.3 t low m s high period of the scl clock 4.0 0.6 t high m s set-up time for a repeated start condition 4.7 0.6 t su:sta m s data hold time 0 (1) 0 (1) 0.9(2) t hd:dat ns data set-up time 250 100 t su:dat ns rise time of both sda and scl signals 1000 20+0.1cb 300 t r ns fall time of both sda and scl signals 300 20+0.1cb 300 tf ns set-up time for stop condition 4.0 0.6 t su : sto ns capacitive load for each bus line 400 400 cb pf
st7263 102/109 7.9 8-bit adc characteristics * note : adc accuracy vs. negative injection current : for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb by 10k w increase of the external analog source impedance. these measurements results and recommandations are done in the worst condition of injection: - negative injection - injection to an input with analog capability ,adjacent to the enabled analog input - at 5v v dd supply, and worse temperature case. oe ge 1 lsb (ideal) 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line tue =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. oe =offset error: deviation between the first actual transition and the first ideal one. ge =gain error: deviation between the last ideal transition and the last actual one. dle =differential linearity error: maximum devia- tion between actual steps and the ideal one. ile =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) tue dle ile (3) v dda v ssa adc analog to digital converter (8-bit) symbol parameter conditions min typ max unit |tue| total unadjusted error* f adc =f cpu =4mhz v dd =v dda =5v 2 lsb oe offset error* -1 1 ge gain error* -2 2 |dle| differential linearity error* 1 |ile| integral linearity error* 2 v ain conversion range voltage v ssa v dda v i adc a/d conversion supply current f adc =f cpu =4mhz v dd =v dda =5v 1ma t stab stabilization time after enable adc 30 s t load sample capacitor loading time 8 32 s 1/f adc t conv hold conversion time 8 32 s 1/f adc r ain external input resistor 20 kw r adc internal input resistor 18 kw c sample sample capacitor 22 pf
st7263 103/109 8-bit adc characteristics (contd) px.x/ainx r ain v ain c pin 5pf v dd v t = 0.6v leakage v t = 0.6v c pin v t leakage c hold ss sampling switch ss at the pin due to various junctions c hold 22.4 pf capacitance = input capacitance = threshold voltage = sampling switch = sample/hold 1a v ss = leakage current
st7263 104/109 8 package characteristics 8.1 package mechanical data figure 45. 34-pin shrink plastic small outline package, 300-mil width figure 46. 32-pin shrink plastic dual in line package, 400-mil width dim. mm inches min typ max min typ max a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.0115 b 0.36 0.48 0.014 0.019 c 0.23 0.32 0.0091 0.0125 d 17.73 18.06 0.698 0.711 e 7.42 7.59 0.292 0.299 e 1.02 0.040 h 10.16 10.41 0.400 0.410 h 0.64 0.74 0.025 0.029 k 0 8 l 0.61 1.02 0.024 0.040 number of pins n34 so34s 0.10mm .004 seating plane 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32
st7263 105/109 figure 47. 32-pin shrink ceramic dual in-line package dim. mm inches min typ max min typ max a 3.63 0.143 a1 0.38 0.015 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.64 0.89 1.14 0.025 0.035 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 29.41 29.97 30.53 1.158 1.180 1.202 d1 26.67 1.050 e 10.16 0.400 e1 9.45 9.91 10.36 0.372 0.390 0.408 e 1.78 0.070 g 9.40 0.370 g1 14.73 0.580 g2 1.12 0.044 l 3.30 0.130 ? 7.37 0.290 number of pins n32 cdip32sw
st7263 106/109 9 device configuration and ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 9.1 device ordering information and transfer of customer code customer code is made up of the rom contents. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all unused bytes must be set to ffh. the customer code should be communicated to stmicroelectronics with the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 48. sales type coding rules table 26. ordering information note 1. /xxx stands for the rom code name as- signed by stmicroelectronics. table 27. development tools st72 t 63 1 k 4 b 1 / xxx family version code sub family subset index number of pins rom size code package type temperature code rom code (three letters) 0 = 25c b = plastic dip 4 = 16k k = 32/34 pins no letter = rom 1 = standard (0 to +70c) d = ceramic dip 2 = 8k e = eprom m = plastic so 1 = 4k t = otp subset index : 1 = fully featured; other number = downgraded versions sales type 1) program memory (bytes) ram (bytes) package st72e631k4d0 16k eprom 512 csdip32 st72631k4m1/xxx 16k rom so34 ST72T631k4m1 16k otp st72631k4b1/xxx 16k rom psdip32 ST72T631k4b1 16k otp st72632k2m1/xxx 8k rom 256 so34 ST72T632k2m1 8k otp st72632k2b1/xxx 8k rom psdip32 ST72T632k2b1 8k otp st72633k1m1/xxx 4k rom 256 so34 ST72T633k1m1 4k otp st72633k1b1/xxx 4k rom psdip32 ST72T633k1b1 4k otp development tool sales type remarks real time emulator st7263-emu2 eprom programming board st72e63-epb/eu st72e63-epb/us 220v power supply 110v power supply
st7263 107/109 st7263x microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference : . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references: device: [ ] st72631k4 [ ] st72632k2 [ ] st72633k1 package: [ ] dual in line plastic [ ] small outline plastic specify conditioning [ ] standard (stick) [ ] tape & reel [ ] die form specify conditioning [ ] inked unscribed wafers [ ] inked and scribed wafers special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 13 characters. authorized characters are letters, digits, '.', '-', '/' and spaces only. we have checked the rom code verification file returned to us by stmicroelectronics. it conforms exactly with the rom code file orginally supplied. we therefore authorize stmicroelectronics to proceed with device manufacture. signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . .
st7263 108/109 9.2 st7 application notes 9.3 to get more information to get the latest information on this product please use the st web server: http://mcu.st.com/ identification description programming and tools an985 executing code in st7 ram an986 using the st7 indirect addressing mode an987 st7 in-circuit programming an988 starting with st7 assembly tool chain an989 starting with st7 hiware c an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1106 translating assembly code from hc05 to st7 example drivers an969 st7 sci communication between the st7 and a pc an970 st7 spi communication between the st7 and e2prom an971 st7 i2c communication between the st7 and e2prom an972 st7 software spi master communication an973 sci software communication with a pc using st72251 16-bit timer an974 real time clock with the st7 timer output compare an976 driving a buzzer using the st7 pwm function an979 driving an analog keyboard with the st7 adc an980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 usb microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 software implementation of i2c bus master an1046 st7 uart emulation software an1047 managing reception errors with the st7 sci peripheral an1048 st7 software lcd driver an1078 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle an1082 description of the st72141 motor control an1083 st72141 bldc motor control software and flowchart example an1129 pwm management for bldc motor drives using the st72141 an1130 brushless dc motor drive with st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1182 using the st7 usb low-speed firmware product optimization an982 using ceramic resonators with the st7 an1014 how to minimize the st7 power consumption an1070 st7 checksum selfchecking capability an1179 programming st7 flash microcontrollers in remote isp product evaluation an910 st7 and st9 performance benchmarking an990 st7 benefits versus industry standard an1086 st7 / st10u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f8
st7263 109/109 10 summary of changes description of the changes between the current release of the specification and the previous one. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com revision main changes date 1.8 changed status of the document (datasheet instead of preliminary data). added section 9.2 and section 9.3 on page 108 . august 00

▲Up To Search▲

Price & Availability of ST72T63

	To Download ST72T63 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .